From 3ce109d2e649ea83495a6b91f38a9e13ba584e98 Mon Sep 17 00:00:00 2001 From: Xiao Wang Date: Fri, 10 Aug 2012 09:03:44 -0300 Subject: [RHEL6 qemu-kvm PATCH 4/9] e1000: conditionally raise irq at the end of MDI cycle RH-Author: Xiao Wang Message-id: <1344589429-3229-5-git-send-email-jasowang@redhat.com> Patchwork-id: 40683 O-Subject: [RHEL6.4 qemu-kvm 4/9] e1000: conditionally raise irq at the end of MDI cycle Bugzilla: 607510 819915 RH-Acked-by: Michael S. Tsirkin RH-Acked-by: Alex Williamson RH-Acked-by: Vlad Yasevich Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=607510 According to the spec: "When set to 1b by software, it causes an Interrupt to be asserted to indicate the end of an MDI cycle." We need check the Interrupt Enable bit and raise irq only when it is set. Signed-off-by: Jason Wang Signed-off-by: Michael S. Tsirkin (cherry picked from commit 17fbbb0b3d0b09f07d288991248c81f441bf6941) --- hw/e1000.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) Signed-off-by: Eduardo Habkost --- hw/e1000.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/e1000.c b/hw/e1000.c index 25f753b..ff92298 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -237,7 +237,10 @@ set_mdic(E1000State *s, int index, uint32_t val) s->phy_reg[addr] = data; } s->mac_reg[MDIC] = val | E1000_MDIC_READY; - set_ics(s, 0, E1000_ICR_MDAC); + + if (val & E1000_MDIC_INT_EN) { + set_ics(s, 0, E1000_ICR_MDAC); + } } static uint32_t -- 1.7.11.2